A System-on-Chip Design of the RadioGatún Hash Function

Recent VLSI hash function designs allow incorporating features such as more complex input expansion schedules, more rounds and bigger states into these functions. As a result, these hash functions are slower and bulkier when compared with previous ones such as MD4, MD5, SHA-1, RIPEMD, etc. An architecture and VLSI implementation of a new hash function called RadioGatún, that achieves high-speed performance, is presented in this paper. Three different FPGA devices are used for the demonstration of this new hash function. In the first device, the hash function achieves throughput up to 1145 Mbps at 85 MHz; in the second device it achieves throughput 1819 Mbps at 135 MHz; in the third device, it reaches a throughput 4406 Mbps at 327 MHz for one data block for hashing. Since no other previous RadioGatún implementations exist in the literature, the comparison with previous implementations of hash families such as MD5, SHA-1, SHA-2, Whirlpool, etc. are provided.